In recent years, integration of virtual machines into a single server has been advancing owing to improvement of the processing ability of servers and enhancement in the virtualization environment. This leads to mass consumption of resources inside the server, such as memories, storages, input/output devices, etc., and it results in shortage of resources. To solve this problem, a technology for expanding external resources has been developed. Signal transmission between a server and external resources is becoming several tens of lanes in size, and the transmission rate is going to increase from the existing rate of around 10 Gbps to up to several tens Gbps in the near feature. It is unrealistic to carry out such a high-rate signal transmission via electric cables in terms of a transmission distance, electricity consumption, and the weight and the volume of cables. For this reason, optical fiber connections are promising.
When using an optical link to transmit bus signals such as PCI-Express Bus signals, control data are transmitted in addition to data signals. FIG. 1A and FIG. 1B illustrate conventional methods to transmit control signals together with optical data signals. In FIG. 1A, an extra lane for control signals is added to the data transmission lanes (optical fibers). With this configuration, control signals are transmitted through the dedicated lane, but the number of channels and the number of fibers of the optical link increase. Besides, the cost increases because of inefficient configuration, where the total number of lanes becomes five if the number of data lanes is four, and becomes nine if the number of data lanes is eight.
In FIG. 1B, a low-frequency signal is superimposed on a data signal. (See, for example, Patent Document 1.) With this method, the low-frequency signal becomes noise components for the high-frequency data signal, and the transmission properties deteriorate. The higher the data rate, the greater the influence of the property degradation is.
To reduce the number of internal wirings of an IC, a known technique indicates logical values using combinations of timings of transition edges of plural signals. (See, for example, Patent Document 2).
Patent Document 1: Japanese Laid-open Patent Publication No. H05-37974
Patent Document 2: Japanese Laid-open Patent Publication No. 2003-32084